Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Table 3

Computation operations and memory by iteration.

					Compare	Memory access
Data and algorithm structures proposed in [17–19]	Horizontal processing			E	2.E	3.E
	Vertical processing	(1 + dv).E	dv.E			4.dv.E + 2.E
	Total computation	(1 + dv).E	dv.E	E	2.E	4.dv.E + 5.E
Proposed optimization		E	E	E	2.E	4.E