Research Article
Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications
Table 5
Decoding performance on Intel Xeon gold 6130 multicore platforms using OpenMP.
| | Matrix sizes | Edge | Z | SNR (dB) | BER | Intel Xeon gold 6130 | Quad-core Cortex-A72 | | Latency (in ms) | CPU number | Latency (in ms) | CPU number |
| | 9216 × 4608 | 29 184 | 384 | 4.5 | 7 × 10–10 | 0.74 | 8 | 2.4 | 4 | | 4608 × 2304 | 14 592 | 192 | 4.5 | 8.7 × 10–10 | 0.48 | 6 | 1.16 | 4 | | 2304 × 1152 | 7 296 | 96 | 4.5 | 2.2 × 10–9 | 0.33 | 3 | 0.56 | 4 | | 1152 × 576 | 3 648 | 48 | 4.5 | 5.2 × 10–9 | 0.24 | 1 | 0.29 | 4 | | 576 × 288 | 1 824 | 24 | 5 | 3.4 × 10–9 | 0.11 | 1 | 0.15 | 4 |
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