Abstract
Digital signal processing (DSP) applications are nowadays widely
used and their complexity is ever growing. The design of dedicated hardware accelerators is
thus still needed in system-on-chip and embedded systems. Realistic hardware implementation
requires first to convert the floating-point data of the initial specification
into arbitrary length data (finite-precision) while keeping an acceptable computation accuracy. Next, an optimized
hardware architecture has to be designed. Considering uniform bit-width specification allows to use traditional
automated design flow. However, it leads to oversized design. On the other hand, considering non uniform
bit-width specification allows to get a smaller circuit but requires complex design tasks. In this paper, we
propose an approach that inputs a C/C++ specification. The design flow, based on high-level synthesis (HLS)
techniques, automatically generates a potentially pipeline RTL architecture described in VHDL. Both bitaccurate
integer and fixed-point data types can be used in the input specification. The generated architecture uses
components (operator, register, etc.) that have different widths. The design constraints are the clock period
and the throughput of the application. The proposed approach considers data word-length information in
all the synthesis steps by using dedicated algorithms. We show in this paper the effectiveness of the proposed
approach
through several design experiments in the DSP domain.