Research Article
An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H
Table 3
Specifications for pipeline ADC stages.
| Spec | Input | Stage 1 | Stage 2 | S&H | 4โbits | 3โbits |
| Sub-ADC error (bits) Offset voltage (mV) | 16 | 6 31.25 | 3 125 | Gain error (%) | 1.6 | 12.5 | โ | DAC error (bits) | โ | 6 | โ | Noise level (dBc) | โ34 | โ34 | โ25 | Clock jitter | 226โps |
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