Research Article
A Virtual Fabrication and High-Performance Design of 65 nm Nanocrystal Floating-Gate Transistor
Table 1
Parameters and conditions of the nanocrystal floating-gate transistor fabrication processes.
| | Fabrication steps | Simulated conditions |
| | -axis from 0 to 0.25 m and spacing 0.03 m (other areas), 0.013 m (channel), and 0.005 m in S/D regions | | -axis from 0 to 1 m and spacing 0.01 m | | Silicon (100) | Dope boron atoms/cm3 | | Epitaxial | Dope arsenic atoms/cm3, 1000°C, and 0.5 m | | P well | Dope boron atoms/cm3 and 100 KeV | | Locos | Conventional | | Tunnel oxide | 890°C and dry oxide | | Channel doping | Doped boron atoms/cm3 and 100 KeV | | Floating gate | 3 nm, dope phosphorus atoms/cm3, and 20 KeV | | Silicon dioxide | 15 nm | | Control gate | 80 nm, dope phosphorus atoms/cm3, and 30 KeV | | Oxide for protecting device | 15 nm | | Aluminum contacts | 18 nm | | Source/drain doping | Dope arsenic atoms/cm3 and 55 KeV Fermi method (1000°C) |
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