Abstract
Wireless communication integration is related to many challenges such as reliability, quality of service, communication range, and energy consumption. As the overall performance of wireless sensor networks (WSN) will be improved if the capacity of each sensor node is optimized, several techniques are used to fine-tune the various circuits of each node. In recent works, the wake-up receiver nodes have been introduced to minimize latencies without increasing energy consumption. To overcome the sensitivity of wake-up receiver limitations, a design of a low-noise amplifier (LNA) with several design specifications is required. This article discusses the relevance of the wake-up receiver in WSN applications and provides a brief study of this component. An LNA design for WSN wake-up receiver applications is presented. The challenging task of the LNA design is to provide equitable trade-off performances such as noise figure, gain, power consumption, impedance matching, and linearity. The LNA circuit is designed for wireless personal area network (WLAN) standards utilizing RF-TSMC CMOS 0.18 μm. Two innovative techniques are applied to the LNA topology to improve its performance: forward body biasing is used to reduce power consumption by 11.43 mW, and substrate resistance is added to reduce noise by 1.8 dB. The developed LNA achieves a noise figure of 1.6 dB and a power gain of 21.7 dB at 5.2 GHz. At 0.6 V, the designed LNA dissipates 0.87 mW.
1. Introduction
The Internet of Things (IoT) is currently at the forefront of converting numerous areas to a degree of smartness by storing and processing data in a distributed manner to increase productivity.
IoT technology is built on powerful wireless devices that are integrated in a complex ecosystem to share and analyze data. These wireless devices are known as sensor nodes, and they are scattered throughout a large network using multiple technologies and communicating at various frequency levels. The operating frequency influences data rate, transmission power, and power consumption in the sensor node.
Wireless technologies such as Wi-Fi, Bluetooth, radio frequency identification (RFID), and ultrawideband (UWB) are used to provide reliable localization in an IoT-based system. As indicated in Figure 1, ultrawideband (UWB) is a digital pulse-based technology for digital data transmission with a bandwidth of 7.5 GHz. It takes a little power to operate over short distances (up to 15 m). Because of its low power spectral density (PSD) of -41.3 dBm/MHz, it may be simply and securely installed alongside current wireless communication systems without generating interference. UWB’s high data rate transmission with low energy consumption and multipath resistance characteristic enables it to be used for high-accuracy wireless range in IoT applications [1].
On the other hand, a WSN system is a layered server architecture in which each layer is defined according to a specific function to perform. Upper and lower layers further divide network architecture into seven different layers (application, presentation, session, transport, network, data link, and physical layers). In literature, many methods and techniques have been introduced in order to minimize the energy of WSN systems. Some researches concentrated on minimizing the energy based on algorithms in the network layer [2, 3]. And other researches are interested in energy consumption at the physical layer as our work.
The wake-up receiver is an important component of wireless sensor networks. This compact receiver is used in a wide range of applications, including IoT, ambient intelligence, and personal area networks. One of the most critical difficulties in wake-up receiver design is lowering power consumption to improve battery life; Figure 2 depicts a wireless sensor node outfitted with a wake-up receiver. A detailed study on wake-up receiver and a comparison of some existing architectures have been presented in [4].
As part of its function, it is expected that the wake-up receiver can demodulate a signal, recognize in some cases a particular code, and issue a pulse to turn on the main receiver chain. As a result, its reaction time is critical since it contributes to the receiver’s and the application’s launch times. A communication protocol with code recognition allows the reduction of incorrect wake-up signals and so optimizes usage. Good reception is dependent on its capacity to identify undesired signals, regardless of its ability to receive weak signals or function in a variety of situations.
The signal is transmitted through an RF carrier whose frequency is an important parameter. The frequency range is chosen based on a variety of parameters. In the scenario when the wake-up receiver and the main receiver are on the same chip, it may be congruent to that of the main radio for simplicity and feature sharing. Because of space and potential coupling, we can use the same frequency to prevent intermodulation difficulties and enable the use of a single antenna. However, if no restrictions are put on the primary receiver, the use of each frequency band is governed by rules. Bluetooth, Zigbee, and other wireless technologies, for example, use the 2.4 GHz range. Working in such a band necessitates a high level of selectivity. Furthermore, the most commonly utilized band in literature [5–7] for the construction of wake-up receivers is 868 MHz; the advantage of this band, in addition to registering in the Zigbee standards, is that it is part of the ISM (Industrial Scientific Medical) band. Using this band relaxes the limits on the communication protocol, but we cannot use those wake-up receivers in UWB, wireless personal area networks (WLAN), body area networks, and other networks.
The previously described frequency band selection influences the modulation technique selection. This modulation is used to transmit data across an RF carrier. The complexity of the modulation is advantageous for signal transmission since it provides immunity when compared to other signals. The latter, on the other hand, will need more complicated circuits and is less consistent with the aim of low consumption. The first modulation approach is frequency modulation, which is difficult to execute in the context of a wake-up receiver because it is impossible to control a reference clock without employing external and active components. Furthermore, the chain design is complicated and incompatible with the goal of low consumption. The second modulation method is amplitude modulation, which has the simplest handling; it consists of multiplying an RF signal, the carrier, by an information signal, the modulating signal. The primary drawback of this modulation is the low signal-to-noise ratio (SNR) and frequency modulation. Amplitude modulation is especially well suited for passive or semipassive reception methods. In this situation, the receiver provides excellent consumption performance. There are two sorts of active reception systems that may be applied. The simplest is the chain with direct detection, which operates with no frequency change, and the more sophisticated is the chain with intermediate detection, which operates with an intermediate frequency. The most significant item in consumption in the first situation is the amplification of the RF signal, whereas the most important item in consumption in the second case is the creation of the intermediate frequency. The phase is the final signal characteristic that may be modified. This sort of modulation is commonly used in telecommunications, such as GSM and Wi-Fi. A complicated infrastructure of mixers, phase shifters, and oscillators is used to demodulate a phase-modulated signal. It is not appropriate for low-power circuits due to its complexity. We identified no realizations based on this modulation in the literature for wake-up receiver-based applications.
Among the required parameters for a wake-up receiver is sensitivity, which must be more than -70 dBm. We can overcome the low-range constraint by developing a highly sensitive receiver. The data rate is another key criterion that is primarily determined by the application, as most IoT applications require a very low rate with very occasional transfers. As a result, lower data rates can be used to reduce power consumption.
Numerous research studies on the application of the wake-up receiver have been published recently. A highly integrated and scalable 65 nm CMOS wake-up receiver was presented and manufactured in 2022 [8]. It achieves a performance of -91.5 dBm sensitivity with a power consumption of 0.9-20.9 μW for 1 s-10 ms latency. However, in [9], the authors designed only an envelope detector for the front end of a wake-up receiver. Two figures of merit to guide the optimization of the trade-offs of a MOS envelope detector for the wake-up receiver have been presented. In [10], a novel approach for low-power WLAN mode employing a wake-up receiver is described. The suggested solution can reduce the issues that emerge when employing a duty-cycling strategy. In [11], the authors present a nanowatt-powered wake-up receiver that is made possible by a number of significant advances. Using a 130 nm CMOS technology, the wake-up receiver achieves -76 dBm at the 151.8 MHz multiuse radio service band and -71 dBm at the 433 MHz industrial, scientific, and medical band with a total DC power consumption of 7.6 nW. In [12], a mixing receiver of the LNA with back gate using a double balance mixer with doublers to merge LNA and LC-resonator quadrature voltage-controlled oscillator from balun circuit was presented. This mixing receiver implemented in the TSMC CMOS process is useful for RF systems.
On the other hand, in [13], the authors proposed a wake-up receiver based on a tuned RF architecture that requires filtering for selectivity and high RF gain for high sensitivity. This architecture fits better due to its simplicity and low cost of implementation; it consists of an LNA to amplify the received signal with minimal noise, an envelope detector to downconvert the RF signal to a baseband with a significantly lower frequency than that of the carrier, a baseband amplifier to boost the voltage level of the extracted envelope, a hysteresis comparator, and a decoder. The PIC12 is chosen for the digital part thanks to its electrical properties, internal peripherals, and space requirements. This wake-up receiver employs a modified medium access protocol that permits 3 μW of power consumption and -90 dB of detection sensitivity. In 2018, Wang et al. and Peter et al. suggested three distinct wake-up receivers [14–16], whose essential design includes a transformer filter, an envelope detector, a comparator, and a digital baseband. In accordance with [14], they use an active envelope detector, and this study presents a 113.5 MHz OOK-modulated wake-up receiver that achieves -69 dB sensitivity while consuming just 4.5 mW of power. Using a passive pseudobalun envelope detector with an LNA, the authors of [15] obtain a sensitivity of -80.5 dBm with just 6.1 nW. Therefore, active envelope detector systems can achieve ultralow power operation, but with limited sensitivity in the absence of substantial RF voltage gain and low-noise baseband circuitry. Using an active pseudobalun envelope detector, Peter et al. [16] accomplish a 400 MHz, 4.5 nW power, and -63.8 dB sensitivity wake-up receiver using this approach. All preceding systems employ the same digital baseband, which is a correlator that analyzes incoming data by calculating the hamming distance between the sequence and the programmable oversampling code. Once the value falls below a certain threshold, the detected pattern is declared and the correlator generates a wake-up signal. Almost all of the previously described wake-up receiver designs operate in a low-frequency spectrum, with some also operating in the 2.4 GHz frequency.
As part of other designs and implementation of the WLAN wake-up receiver, we focus on the design of a low-power LNA using RF-TSMC CMOS 0.18 μm technology. The LNA is an important block in the receiver chain, since it significantly increases the receiver sensitivity, and its performance is a challenge for RF circuit designers. As the LNA is the first component in the signal reception chain that receives the signal after the antenna, any noise created by this amplifier will be carried throughout this chain, affecting the performance of subsequent components; therefore, it is vital to take this parameter into account. As depicted in Figure 3, the LNA amplifier is used to amplify the signal received from the antenna without adding noise. In the case of long-distance communication, such as satellite communication, where waves are transmitted over unguided propagation lines tens or hundreds of kilometers long, the front components must meet the strict requirements that a good link between the different agents of each link requires. In this case, the front-end transistors of the amplifier must be able to meet these requirements. In addition, several research studies focusing only on the LNA’s implementation have been published [17–21].
The rest of the paper is organized as follows: in Section 2, low-noise amplifier design is discussed. The S-parameters, harmonic balance, and Monte Carlo and PVT simulation results of the designed circuits are presented in Section 3. Section 4 concludes the paper.
2. Methods
2.1. LNA Implementation
Figure 4 illustrates the topology of the proposed LNA. It consists of two stages with resistive shunt-shunt feedback. The common-gate topologies and are positioned as the input stage in order to decrease power consumption and generate a broad input match throughout the frequency range of interest. Due to the trade-off between input matching and gain in the common-gate stage, a common-source stage is added to achieve high gain. A shunt-shunt feedback structure is used to adjust the gain by changing the feedback resistance, providing a gain that is continuously varied. is connected to the gate of , and no further driving current is necessary.
By utilizing inductors as shunt inductive peaking and series inductive peaking, respectively, the bandwidth of interest is increased. The capacitances are employed for DC bias isolation.
The input stage is formed of the and transistors. Consequently, the and transistors are used to minimize the main noise source, . Recognizing that each transistor has a unique noise figure, we used and resistors to reduce the noise figure of each transistor, hence lowering the noise figure of the entire circuit.
2.2. Input Matching
The Chebyshev filter has the benefit of a sharp roll in the factor stop band and ripples in the pass band. This filter resonates the input impedance reactive portion across the operational frequency range. Numerous studies utilizing a Chebyshev filter in the LNA implementation design have been published. In [22], a simple Chebyshev filter is used to match the input bandwidth. This input network is less complicated and has an excellent reflected coefficient between 3.1 GHz and 10.6 GHz. As the input stage in [23], a Chebyshev filter has been built with the goal of providing the appropriate higher-end and lower-end cutoff frequencies.
In addition, a Chebyshev filter was employed in [24] to get wideband input matching and flat gain. Figure 5 depicts the used filter.
2.3. Low-Voltage Technique Analysis
Forward body biasing is applied to reduce the transistor’s the T is a V index voltage. The lowering of the T is a V index enables low the DD is a V index operation and enhances circuit design freedom. According to the simulation, the transistor consumes the most power; thus, forward body biasing will be applied to this transistor.
of NMOS can be expressed as follows: where is the threshold voltage with zero-body-source voltage, is the body effect coefficient, and is the bulk Fermi potential. In this brief, the voltage between the body and the source of the transistor is biased reversely V for reducing . According to the simulation, The T is a V index of an NMOS transistor can be lowered to 0.38 V when the body-to-source voltage is equal to 0.45 V. As a result, the supply voltage and power consumption are reduced.
2.4. Noise-Reduction Technique Analysis
To analyze the noise figure of the designed LNA depicted in Figure 4, the noise equivalent circuit without and consideration is shown in Figure 6.
The designed LNA total noise figure is given as follows:
We may assume that, with the exception of and , all transistors have an influence on the overall noise figure; thus, we want to minimize the noise figure of each concerned transistor in order to reduce the total noise figure.
is a substrate resistor that may be used to minimize noise in a MOS device and hence improve the noise performance of the LNA.
Figure 7 depicts a schematic of MOS transistors with a substrate resistance . The noise equivalent circuit of a MOS device with substrate resistance is shown in Figure 8.
(a)
(b)
Generally, the substrate impedance can be simplified to a simple series RC circuit as follows:
So, the substrate resistance is expressed as follows:
The noise figure can be expressed as [25]
The minimum noise figure and the noise parameter can be written as
From Equation (3), adding a substrate resistor increases the substrate impedance . According to Equations (6) and (7), increasing the equivalent substrate resistor decreases the minimal noise figure ; moreover, decreasing and reduces the noise figure in Equation (5).
2.5. Gain Control Circuit
The gain control structure is depicted in Figure 4 at the second stage. We can change the gain by adjusting , the bias voltage. It should be noted that is placed at the gate of and may be written as
Taking into account that is a PMOS transistor and according to Equation (8), the transimpedance gain is controlled by decreasing .
3. Simulation Results
3.1. S-Parameter Simulation Results
Using ADS, the suggested LNA is developed and simulated in the RF-TSMC CMOS 0.18 μm technology. We applied the existing ADS optimization algorithm. We may establish our targets, the type of optimization, and eventually the range of the required optimized parameters using this approach. The circuit uses 1.45 mW of direct current electricity and has a supply voltage of 0.6 volts. The circuit is optimized with the primary objective of reducing noise, giving a high gain and good input matching, and retaining acceptable circuit parameter values in consideration.
Table 1 shows the optimized inductor values, whereas Table 2 shows the optimal capacitance values. It should be noted that the inductance and capacitance values should be as low as feasible in order to be implemented.
The transistor LNA’s needed design characteristics are shown in Table 3. By selecting a minimum transistor length of 0.18 μm, the LNA’s bandwidth is raised and the parasitic capacitors are minimized.
The S-parameter analysis is carried out between 5 and 6 GHz. For the remainder of the simulations, we will concentrate on the results at 5.2 GHz, since the ISM band specification for the IEEE 802.11a in the WLAN standard was adopted for the carrier frequency 5.2 GHz, as shown in Figure 1. Due to the requirement for a greater transmission rate, 802.11b with 11 Mbit/s is clearly inferior to 802.11a, which is a modification to the IEEE 802.11 protocol that adds a higher data rate of up to 54 Mbit/s utilizing the 5.2 GHz band [19].
The simulated input reflection coefficient S11 is shown in Figure 9. S11 equals -14.15 dB at 5.2 GHz.
The reverse isolation is shown in Figure 10. At 5.2 GHz, the S-parameter coefficient S12 is smaller than -21.8 dB. The gain power is equal to 21.7 dB at 5.2 GHz, which is illustrated in Figure 11.
Figure 12 illustrates the simulation results for the noise figure. The proposed LNA exhibits a minimum noise figure of roughly 1.6 dB at 5.2 GHz.
The S-parameter simulations of the proposed LNA are shown in Figures 9–12. Based on this analysis, we may conclude that the suggested design presents better performances than several existing circuits in the literature.
3.2. Harmonic Balance Simulation Result
We used the harmonic balance simulation to validate the designed LNA. To calculate intermodulation distortion products and third-order interception point, two-input tones of the same strength but separated by a very short frequency offset or spacing can be employed. At various mixing frequencies, these two tones combine and produce higher-order distortion products.
As seen in Figure 13, the value of the IIP3 point is equal to -26.5 dBm which represents a good linearity for such a nonlinear device.
To compare the performances of the LNAs, the figure of merit (FoM) is calculated as defined in [26]:
Table 4 compares the proposed LNA’s circuit performance to that of various earlier published researches.
3.3. Monte Carlo Simulation
A series of Monte Carlo simulations were done to demonstrate the impact of process modifications on the performance parameters of the LNA. The Monte Carlo analysis was used to reduce the size of all circuit transistors by 5%.
Figures 14 and 15 show the results of the Monte Carlo analysis. The gain parameter of the LNA is shown in Figure 14, which is more than 14.9 dB for 200 Monte Carlo simulation runs at 5.2 GHz. The noise figure parameter of the LNA is less than 2 dB for 200 Monte Carlo simulation runs in the same frequency range, as shown in Figure 15.
3.4. PVT Simulation
The performance of this LNA was evaluated at various process corners, supply voltages, and temperatures to assess its sensitivity to PVT variations. Gain and noise figure are the factors evaluated for PVT adjustments. The process corners used in this simulation were given by the foundry.
First, three cases were considered: the first (TC) is the most typical case, in which all of the transistors have a typical model and the circuit operates at 0°C. The second case (WP) considers operating circumstances where the temperature is -45°C and the models of all transistors conform to the FF (fast-fast) model. The transistors in the third case (WS) employ the SS (slow-slow) model, and the temperature is around 50°C.
At 5.2 GHz, the PT (Process-Temperature) change has no influence on the power gain value, as illustrated in Figure 16. While temperature has little influence on the noise figure value (Figure 17), it is still less than 2 dB for different temperatures.
Knowing that lowering the supply voltage is a way used in this article to minimize power usage, the values examined were 0.7 V, 0.6 V, and 0.55 V.
As shown in Figure 18, at 5.2 GHz, the supply voltage variation has little effect on the power gain value, but the minimum gain value is about 21 dB. However, the supply voltage variation has no effect on the noise figure value (Figure 19).
4. Conclusion and Future Works
The presented work describes a low-power WLAN LNA for WSN wake-up receiver applications. The system is designed to give more importance to the reduction of power consumption and noise figure. Implemented in a 0.18 μm CMOS technology, the suggested LNA consumes 0.87 mW. The maximum gain attained at 5.2 GHz is approximately 21.7 dB. The minimum noise level is around 1.6 dB as a high substrate resistance is used to reduce the noise figure. Corner simulations are done to observe the circuit’s immunity to PVT changes as well as Monte Carlo simulations to prove the performance of the LNA. It can be concluded from the analysis that our design has presented advantages in almost all performance parameters. Hence, the circuit is suitable for applications which need low power consumption, low noise, and low-cost solution for WSN wake-up receivers. In future work, we intend to develop the entire WLAN wake-up receiver architecture for WSN applications.
Data Availability
The data used to support the findings of this study are available from the corresponding author upon request.
Disclosure
This work is under a PhD project which is not financed.
Conflicts of Interest
The authors declare that they have no conflicts of interest.